www.iterrac.com IT4005D 12.5 gb/s gaas mmic d flip-flop (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4047 rev 0 1 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 description features the IT4005D is a high-speed d-type flip flop fabricated using 1- m hbt gaas technology. its high output voltage, excellent rise and fall time and the high eye diagram quality at all clock frequencies makes the IT4005D suitable for very high speed and complex digital applications such as decision circuits, waveform shaping, r egister implementation, and timing adjustment. the device consists of a master-slave latch designed using an ecl topology guarantee high- speed operation. the data and clock inputs and dat a outputs are dc coupl ed. at the data input port, the IT4005D tolerates a wide range of oper ating conditions, and the internal 50-ohm resistors avoid the need for external terminations for impedance matching. the IT4005D uses scfl i/o levels and allows either single-ended or differential data in put and output. for the clock, a single-ended, dc-coupled input with an internal 50-ohm resistor followed by a dc block is provided. an amplitude of 700 mv peak-to- peak for the clock is recommended, although depending on the operating frequency, a lower amplitude may be usable. an on-chip output buffer provides an excellent eye diagram at a 12.5 ghz clock frequency. ? 2-13 ghz clock frequency range ? 900 mvpp single ended output dynamic ? output rise time (20%-80%): 25 ps ? output fall time (20%-80%): 24 ps ? dc coupled clock input ? dc coupled data input device diagram ? 50 ohm matched dc-coupled data output ? differential or single-ended inputs ? low power consumption: 1 w at -5.2 v (vqh = 0.0 v, vql = -0.9 v) 0.7 w at -4.5 v (vqh = 0.0 v, vql = -0.6 v) 0.5 w at -4.0 v (vqh = 0.0 v, vql = -0.4 v)
www.iterrac.com IT4005D 12.5 gb/s gaas mmic d flip-flop (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4047 rev 0 2 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 c 150 -65 storage temperature tstg c 125 -15 operating temperature range ? die ta v 1.2 -1.2 data/clock input voltage level, low level vdl v 1.2 -1.2 data/clock input volta ge level, high level vdh v 0 -5.5 power supply voltage vee unit s max. min. parameters/conditions symbol v 0.7 clock input voltage (single-ended, peak-to-peak) vclk v 0 clock input voltage common mode vclkdc v 0.5 data input voltage level (single-ended, peak-to-peak) vinpp v 0.1 0 -0.4 data dc input voltage common mode vindc v -5.0 power supply voltage vee c 85 0 operating temperature range ? die ta units max. typ. min. parameters/conditions symbol absolute maximum ratings recommended operating conditions timing diagram stresses in excess of those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions above those indicated in the operational section of this document is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
www.iterrac.com IT4005D 12.5 gb/s gaas mmic d flip-flop (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4047 rev 0 3 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 electrical characteristics w 0.925 power dissipation pd ma 185 power supply current ic ps 0.9 rms jitter jrms ps 5 peak to peak jitter jpp db 10 minimum output return loss (up to 13 ghz) rlout db 10 minimum input return loss (up to 13 ghz) rlin gb/s 13 12.5 2 input data rate (6) rmax ghz 13 12.5 2 clock frequency (6) fmax deg 290 phase margin at 10.7 gb/s nrz input (5) pm2 deg 224 phase margin at 12.5 gb/s nrz input (5) pm1 ps 12 minimum hold time th ps 12 minimum setup time ts ps 35 output rise delay (clk vs. q,qb) (4) tdh ps 33 output fall delay (clk vs. q,qb) (4) tdl ps 24 output fall time (20% - 80%) tf ps 25 output rise time (20% - 80%) tr v -0.4 -0.85 -1.1 data output voltage amplidude low vql v 0 0 -0.05 data output voltage amplidude high vqh v 0.25 0 -0.75 dc input voltage (with dc-coupled input) (3) vindc 2.0 1.0 0.50 data/clock input voltage level differential peak to peak vinppd v 0.6 -0.25 -1 data input voltage level, low level (single ended) (2) vdl v 0.6 0.25 -0.6 data input voltage level, high level (single ended) (2) vdh v 0.2 0 -0.2 input clock voltage common mode vclkdc v 1.0 0.7 0.5 input clock voltage amplitude vclk v -4.00 -5.0 -5.45 power supply voltage vee units max typ min parameters symbol 1. electrical characteristics at ambient temperature. 2. minimum and maximum values for vdh and vdl have to be set in order to satisfy the following rule: 0.2 v <(vdh - vdl) <1 v 3. in case of single- ended input, the unused one must be tied to vindc which must be nominally set to the applied input mean value. 4. output change state on input rising edge. 5. calculated as follows in the following equation: 6. duty cycle 50%. asymmetrical duty cycle may reduce maximum frequency. pm[deg] = pm(measured) [ps] bitduration [ps]* 360 [ps] where: /s] bitrate[gb 1 n[ps] bitduratio =
www.iterrac.com IT4005D 12.5 gb/s gaas mmic d flip-flop (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4047 rev 0 4 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 eye diagram performance qq\ qq\ qq output at 12.5 gb/s. power supply = -5.2 v output at 10.7 gb/s. power supply = -5.2 v output at 12.5 gb/s. power supply = -4 v
www.iterrac.com IT4005D 12.5 gb/s gaas mmic d flip-flop (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4047 rev 0 5 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 eye diagram performance ( cont.) recommended operational setup qq\ output at 12.5 gb/s. power supply = -4 v bias conditions connect inputs apply -5.0 v at vee apply rf signals to the inputs tune vindc for optimal eye diagram in case of single- ended input.
www.iterrac.com IT4005D 12.5 gb/s gaas mmic d flip-flop (advanced information) this is an advanced data sheet. see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4047 rev 0 6 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 recommended chip mounting pad positions and chip dimensions chip size: 1600 m 10 m x 2335 m 10 m edge to edge chip thickness: 104 m 3 m pad size: 100 m x 100 m rf pad pitch: 150 m unlabeled pads are ground and may be left floating
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